1. Field of the Invention
The present invention relates to an apparatus and method for fabricating a semiconductor device, and more particularly, to a method of testing a semiconductor chip for defects and a testing jig used in the method.
2. Description of the Related Art
In recent years, the capacity of memory cards has increased. As a result, portable devices such as mobile phones, PDAs and portable PCs have become smaller and thinner. Multi-chip packages (MCPs), in which a plurality of packages can be stacked in an area equal in size to that required by a conventional single package, are being mass-produced. Some MCP memory devices include at least three metal interconnecting layers.
FIG. 1 is a photograph illustrating defects present in a cross-section of a conventional semiconductor chip 32 (see FIG. 2). Referring to FIG. 1, the semiconductor chip 32 includes a front surface 10 on which a first metal interconnecting layer 12 and a second metal interconnecting layer 14 are formed and a rear surface 20 opposite the front surface 10. For convenience, a portion of the semiconductor chip 32 on which the first and second metal interconnecting layers 12 and 14 are formed is referred to as the front surface 10.
In FIG. 1, two metal interconnecting layers are illustrated. However, three or more metal interconnecting layers may be formed. A defect “a” is present in the first metal interconnecting layer 12 of the front surface 10, and a defect “b” is present in the second metal interconnecting layer 14 of the rear surface 20. The defects “a” and “b” cause a leakage current in the semiconductor chips 32.
FIG. 2 is a perspective view illustrating a conventional method of testing the front surfaces 10 of the semiconductor chips 32 for defects (for example, the defect “a”). FIG. 3 is a perspective view illustrating a conventional method of testing the rear surfaces 20 of the semiconductor chips 32 for defects (for example, the defect b).
Referring to FIG. 2, the semiconductor chips 32 are formed on a wafer 30 on which an electrical memory test has been performed. A test substrate 40 is placed above the wafer 30, and a plurality of contact pins 42 for signal processing are arranged on at least one side of the test substrate 40. Probe pins 44 at the center of the test substrate 40 protrude toward the wafer 30 and transmit external signals to the semiconductor chips 32. A detector 50 detects, for example, hot electrons emitted from the front surfaces 10 of the semiconductor chips 32.
Referring to FIG. 3, the wafer 30 supported by a support board 60 is placed above the test substrate 40 and is covered by an infrared lens 70. The detector 50 detects hot electrons emitted from the rear surfaces 20 of the semiconductor chips 32.
The conventional method of testing the semiconductor chips 32 has a number of problems. First, the method can be used to test the semiconductor chips 32 in units of wafers, but not in units of chips. Also, while a simple setup process is required to test the front surfaces 10 of the semiconductor chips 32, it takes a considerable amount of time to perform the necessary setup for testing the rear surfaces 20 of the semiconductor chips 32. As a result, it is difficult to sequentially test the front and rear surfaces 10 and 20 of the semiconductor chips 32. Conventional test equipment is believed to be not capable of sequentially testing the front and rear surfaces 10 and 20 of the semiconductor chips 32.